The present invention relates to a clock phase adjusting system, and especially to a system for adjusting a clock signal in an information processing system.
Usually, the main functions of an information processing system, such as operational processing, information holding, etc., in a central processing unit (hereinafter called CPU) can be achieved by a logic circuit formed by semiconductor elements.
This logic circuit is realized by combining many combination circuits, such as OR/NOR gates, and sequential circuits formed by registers, latches, flip-flops (hereinafter called FF) etc., with a plurality of other combination circuits.
The above-mentioned combination circuits can obtain an output signal only by an operation delay time in each element, but in a sequence circuit, the output signal can be obtained when the input data is set by another clock signal, after the input data is applied.
In the usual CPU etc., as is well known, usually a synchronizing system using a clock signal having a constant period is used.
Recently, in accordance with the propagation and development of information processing systems, devices must be manufactured with a small size and at a low cost. On the other hand, if an improvement of a throughput of the CPU etc., is required, then a system having a high speed and large scale must be formed.
Conventionally, a high speed and large scale information processing system is obtained by improvements of system designs, high speed semiconductor elements, and better integration techniques, that is, the realization of a large scale integration circuit (LSI).
The large scale integration circuit provides a high integration with a low cost, and further the above-mentioned logic circuit can be realized with a uniform operational characteristic and high reliability.
The high speed and large scale system is, however, formed by the above-mentioned combination circuit using a large number of semiconductor elements. Therefore, because many semiconductor elements are integrated in the logic circuit, and these elements inevitably have varying operational characteristics, especially the operation time, there is an inevitable slight affect on a margin of the timing of a clock signal in the CPU, etc.
Further, the high speed of the information processing system becomes such that the delay times due to wiring lengths cannot be neglected. Therefore, in the present state, the clock signal of the logic circuit is obtained by distributing a plurality of clock signal having a predetermined delay time via a so-called phase adjusting circuit.
In this case, in the logic circuit distributes the delayed clocks, a clock delay which is inherent to each logic circuit is required. Therefore, in the above-mentioned phase adjusting circuit, a clock signal having a desired delay period must be supplied in accordance with the logic circuit for supplying the clock.
However, in the large scale integration circuit having a conventional phase adjusting circuit, the number of gates included therein is restricted, and further, the number of external draw out terminals in a printed circuit board is also restricted. From this point of view, preferably the number (n) of the terminals of the above-mentioned phase adjusting circuit is restricted, and therefore, the problem arises of a conflict in the coexistence of such a circuit in the LSI.
Further, from the viewpoint of the package in the high density arrangement of the printed circuit board, etc., mounting the LSI mentioned above, it is not desirable from the viewpoint of reliability that the connections in the selected terminal be changed.
That is, .circle.1 if a connection change is attempted by using a short circuit, space for the short circuit is required in the package, and the package efficiency is decreased. .circle.2 If the connection change is attempted by using a wiring change, the operating efficiency is decreased. .circle.3 The short circuit or wiring change causes a problem in the reliability of the connecting terminal.